ECM P/N 5174 Clock card provides frequency generation using
an Analog Devices AD9851 DDS, direct digital synthesis, chip. The DDS output
frequency is 0 to 45MHz output programmable in steps of 0.028 Hz assuming a
20MHz clock source. Additionally, programmable phase adjustment is possible.
The DDS has four direct outputs three outputs go to the I/O
connector, a 1 volt peak Sine wave output, a LVDS output and a 3V TTL output.
One output a 3V TTL output is routed back to the FPGA on the ECM carrier card.
All four outputs are at the same frequency. These are shown in RED.
The clock source for the DDS comes from the FPGA on the
ECM carrier card, this is shown in RED.
The FPGA on the ECM carrier card can mux a number of clock
sources to the DDS including, 1) the 20MHz VCO, 2) a LVDS clock input from the
I/O connector, 3) a TTL clock input from the I/O connector, 4) two RS-485 clock
inputs from the I/O connector and 5)whatever local clocks are available on the
ECM carrier card.
The on board 20Mhz VCO has a +/- 50 ppm absolute pull
range. The VCO is adjusted by a 12 bit DAC providing fine frequency adjustments
for time synch operations.
A temperature sensor is provided for frequency
compensation vs. temperature.
A serial identification circuit prevents use with
incorrect FPGA IP
In the example below The DDS clock input is connected to
the 20MHz reference clock by the FPGA on the carrier card. The DDS is
programmed for 10.10 MHz and this frequency is output in five forms, back to the
FPGA on the ECM carrier, as a 1V sine wave to the I/O connector, as a 3V CMOS
output to the I/O connector and as an LVDS output to the I/O connector.
Indirectly the 10.10MHz is routed inside the FPGA to one of the RS-485 I/O lines
enabled as an output.
Datasheet
http://www.technobox.com/Datasheet-ECM-5174-Clock-4pgv1-A80401-press.pdf
micro mezzanine system electrical conversion module miscellaneous adjustable
variable clock source voltage controlled oscillator sine Technobox 5174
