Product Information

The FlexATX Development Platform provides two PrPMC and three edge-finger PCI bus slots in a standard 9”x7.5” form-factor used in Personal Computer ATX enclosures. One of the two PrPMC slots must be populated with a Processor PMC (VITA 32) and a jumper on the ATX carrier selects monarch mode. The other PrPMC site can be depopulated with a standard PMC (IEEE 1386.1), or populated with a second PrPMC operating in non-monarch mode. The board supports a 64-bit PCI bus connection between all the bus members, except for one of the PCI edge finger slots which supports 32-bits. All slots are keyed for 3.3V signaling (5V signaling is NOT supported). The bus will run at 66 MHz if all the populated PCI bus devices assert “M66EN”, or at 33 MHz if any one of the populated PCI bus devices has M66EN tied to GND.

A 34-bit Floppy Disk connector (JP2) and a 40-pin IDE connector (JP10) are wired to PrPMC slot A rear I/O for use with the Technobox, Inc. P/N 3797 GEODE™ Processor PMC. This slot may be used for other PrPMCs as well if the Rear I/O is not used. A PrPMC populated in Slot B connects to a 96-pin DIN connector of a VMEbus board per the IEEE 1386 recommendations. Fans located under the PrPMC slots provide forced air-cooling. The fans blow air out of the side for efficient non-stalling transport of air at about 4 cubic ft/min. A 7-channel rotational priority circuit arbitrates the REQ signals coming from the PCI devices and issues GNT signals accordingly. The arbiter provides overlapped arbitration, and the last successful member granted the bus becomes the lowest priority device for the next arbitration cycle. Note that each PrPMC requires two REQ/GNT pairs in order to service the PrPMC primary and secondary PCI devices. A logic analyzer header allows observation of the REQ/GNT activity.

LED logic decodes the PCI bus command field to illuminate LEDs for Memory, Configuration, and I/O accesses. Pulse stretching is used to power LEDs for infrequent events. Other LEDs monitor power, PCI Interrupt, and bus mastering slot activity. For LEDs located on the cabinet, a header is provided to drive the Activity LED (PCI bus activity in this implementation) and Power LEDs. The Power Switch and Hard Reset buttons are also supported. For JTAG support, the circuit will electronically bypass depopulated slots to preserve the TDI-TDO chain. The JTAG terminates in a 10-pin header pinned for ALTERA ByteBlasterMV applications (3.3V). This facilitates in-circuit programming of user circuits on the PCI plug-in modules. Power is provided to the board via a standard 20-pin ATX power supply connector. A linear regulator power the +3.3aux rail to the PCI and PrPMC slots from the ATX +5Vaux supply. This board has been carefully designed using an 8-layer PCB, with 4 signal layers and 4 power planes. PCI signals are controlled at 75 ohms. The PCI clocks are routed with equidistant paths. These practices assist in supporting operation at 66 MHz.

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